Intel Sr. Pre-Si Verification Engineer in Santa Clara, California

Job Description

Come join Intel's Scalable Performance CPU Development Group SDG as an IP Engineer working on exciting products fueling the data center growth! We are seeking an experienced validation engineer to work with a diverse team designing Intel's next generation IP for High Performance Computing and Artificial Intelligence products.

Responsibilities:

Identification, definition, development and deployment of verification/validation environment of complex design components

Determine architecture for validation for chip and system simulation/emulation. Defines module interfaces/formats for simulation.

Design and build test benches for design under test.Identify, document and execute test plans, develop and debug random constrain verification test suite to fully verify the design under test

Experience with pre-silicon validation of designs which include processor cores and custom logic working together.

Strong independence and proven ability to set and meet own goals

Ability to work effectively with both internal and external teams/customers is expected.

Qualifications

Minimum qualifications:

MS degree in EE or ECE or CS Engineering with 7-8 years of industry experience.

Experience with Computer Architecture or pre-Si verification.

Experience with Logic Design verification

Experience with Microprocessor or Chipset design methods.

Experience with pre-Silicon simulation tool flows required.

Example tools include but not limited to:- Synopsys VCS, Verdi and DVE

Strong Knowledge of UVM including developing verification test benches and constrained random validation.

Experience with modern CPU architecture, such as memory cache hierarchy, scheduler, pipeline

Ability to work effectively with both internal and external teams/customers is expected.

Possess excellent written and interpersonal skills

Strong collaboration and interpersonal skills

Additional desired skills:

Ability to create and execute test plans for wide feature set.

Ability to debug and root cause failure signatures at RTL level.Scripting and tool flow automation knowledge, such as Python/Perl, C.Knowledge and familiarity with FPGA prototyping as a pre-silicon validation vehicle would be a plus .

This is an Intel Federal Position

This position involves work on a U.S. Government contract which may impose certain security requirements. The government may require that you certify your citizenship status. If you are not a U.S. citizen, the government may require you to pass a security check before you can be approved to work on the project. Please note that any offer by Intel for this position is conditioned upon meeting and/or passing the U.S. Government's security check requirements should the government impose these requirements.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Other Locations

US, Oregon, Hillsboro

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